The invention relates to gallium arsenide (GaAs) integrated circuit fabrication technology, and more particularly, to a method of forming on a GaAs substrate an insulated GaAs-gate field effect transistor (FET) having self-aligned source/drain and submicron channel length.
Since the mobility of electrons is substantially higher in GaAs than in silicon, higher integrated circuit performance can be achieved using GaAs as the substrate material compared to silicon for an equivalent power consumption. A number of transistor types have been built using GaAs material. The most common and commercially successful type is the metal-semiconductor field effect transistor (MESFET). This device comes in two forms: the depletion mode MESFET (D-MESFET) and the enchancement mode MESFET (E-MESFET). The basic MESFET consists of a metal Schottky gate placed between a source and a drain region. The transistor typically is formed in two ion-implantation steps: a relatively low concentration implant below the gate region provides the channel, and a relatively high concentration implant in close vicinity to the gate provides the source and the drain regions. In a D-MESFET, with no voltage applied to the gate, current flows through the channel between the transistor's source and drain when a voltage is applied across the source and drain. The application of a gate voltage (negative with respect to the source) causes the channel to become narrower, reducing current flow. If a sufficiently negative gate voltage is applied, the current flow is pinched off. In an E-MESFET, the region under the gate is doped such that the channel is pinched off when no gate voltage is applied. A small positive gate voltage with respect to the source will initiate current flow.
Another GaAs device that has shown potential for commercialization is the high electron mobility transistor (HEMT). This structure has also been termed as the selectively doped heterojunction transistor (SDHT), modulation doped FET (MODFET) and two-dimensional electron gas FET (TEGFET). These are superlattice heterojunctions in which layers of gallium-aluminium-arsenide (AlGaAs) are typically deposited on an undoped GaAs channel. One such device was disclosed in an article by T. Mimura et al, entitled "A New Field Effect Transistor with Selectively Doped GaAs/n-GaAl.sub.x As.sub.1-x Heterojunctions", Japanese Journal of Applied Physics, Vol. 19. No. 5, pages L225-227 (May 1980). The device described in this article consists of a pair of undoped GaAs layers sandwiching a layer of silicon doped GaA1As. A Schottky gate is provided by the deposition of aluminum on the surface of the top undoped GaAs layer. Electron mobility in a HEMT is higher than a MESFET as the charge carriers are not scattered by dopant ions in the channel. By raising gate voltage just above the threshold, a HEMT quickly reaches its full transconductance, giving it a very fast turn-on time. However, the threshold voltage of a HEMT is neither as controllable nor as low as is desirable for logic circuits with reduced power supply voltages. The threshold variability is due to its sensitivity to the doping and thickness of the active layer. Also, the particular layered structure of the HEMT in combination with the Schottky contact to the top results in a threshold voltage which departs significantly from the desired near-zero value.
To overcome the deficiencies of the HEMT, a new semiconductor-insulator-semiconductor transistor has been proposed in U.S. patent application Ser. No. 454,741, entitled "A Double Heterojunction FET with Ohmic Semiconductor Gate and Controllable Low Threshold Voltage" by J. Rosenerg which is assigned to IBM Corporation, the present assignee. This structure consists of a heavily doped n-type GaAs gate with undoped AlGaAs as the gate insulator, on an undoped GaAs layer. Threshold voltage of this device structure is naturally near zero since the work function difference between the doped GaAs gate and the undoped GaAs is essentially zero. This structure is well suited for low-voltage logic applications. Another advantage of this structure is that, at least to first order, its threshold voltage is independent of the thickness and aluminum mole fraction of the AlGaAs layer. This undoped heterojunction structure is inherently more resistant to high-temperature annealing, not suffering from a field-enhanced degradation of the heterojunction due to ionized impurities.
Despite these advantageous features of the GaAs-gate heterojunction FET, the prior art methods of fabrication provided a structure having a rather large gate length. For example, the article by P. M. Solomon et al, entitled "A GaAs Gate Heterojunction FET", IEEE Electron Device Letters, Vol. EDL-5, No. 9, pages 379-381, September 1984 discloses an N type GaAs-gate FET having a gate length of 1.5 .mu.m. The article by K. Matsumoto et al, entitled "n+ GaAs/Undoped GaAlAs/Undoped GaAs Field-Effect Transistor" Electronics Letters, 1984, 20, pages 462-463 discloses a method of forming a GaAs gate of length 2 .mu.m. Likewise, the article by K. Matsumoto et al, entitled "p-Channel GaAs SIS (Semiconductor-Insulator-Semiconductor) FET", Electronics Letters, 1985, 21, pages 580-581 discloses a P channel GaAs gate FET having a gate length of 2 .mu.m. The basic reason for such large dimensioned gate structures is that these prior art methods utilize standard photolithography and etching techniques to form the gate. These methods are thus not suitable for fabrication of submicron-length gate structures that are demanded by high-density and-speed GaAs memory and logic circuits. Another shortcoming of some of these prior art structures is that the metal contact to the GaAs gate tends to be sufficiently away so as to appreciably increase gate resistance. Yet another disadvantage is that these prior art methods obtain a structure wherein the source/drain is either too far away from the gate, leading to increased source/drain resistance, or too close to the gate leading to increased gate-source/drain overlap capacitance. From a performance standpoint, it is imperative that the source/drain be located at an optimal distance from the gate which permits minimization of both source/drain resistance and gate-source/drain overlap capacitance. As device dimensions shrink to submicron dimensions, this optimization becomes even more important.
It would appear that a submicron-length GaAs gate FET may be realized by utilizing submicron E-beam lithography to define the gate. However, existing E-beam systems require an E-beam pattern generator, sophisticated E-beam optics and custom software to control, all of which render this technique prohibitively expensive.
Accordingly, it is an object of the present invention to provide a method of forming a GaAs-gate heterojunction FET which has submicron-length gate and self-aligned metal contacting the gate.
Another object of the invention is to provide a method of forming a high-speed GaAs-gate FET by minimizing the source/drain resistance and gate-source/drain capacitance.